Charlotte Convention
Center, Charlotte,
North Carolina
October 2-3, 2003
Sponsored
by -
TTTC - The IEEE Computer Society Test Technology Technical Council
In
Conjunction with -
Internation Test Conference / Test Week 2003
Scope:
The higher level of
manufacturing susceptibility and field reliability
in today's SoC require enhanced detection, diagnosis and yield
optimization solutions. These solutions necessitate incorporating
on-chip infrastructure IP blocks, in addition to the functionality
of the SoC. The Infrastructure IP leverages the manufacturing knowledge
and feeds back the information into the design phase. This workshop
analyzes this key trend and gives the chance to describe a range of
infrastructure IP for today's System-on-Chip (SoC) designs. This
includes infrastructure IP for test, diagnosis, timing measurement,
debugging, test, repair, and fault tolerance.
Workshop
at a glance:
Thursday, October 2, 2003
---------------------------------------
02:00pm-05:00pm Registration
04:00pm-04:30pm Opening Session
04:30pm-06:30pm Session 1: Advanced I-IP Solutions for Embedded Memory
Yield Improvement
07:00pm-09:00pm Evening Reception
Friday,
October 3rd, 2003
-------------------------------------
07:00am-08:00am Continental Breakfast
08:00am-10:00am Session 2: Embedding I-IP for Configuration, Measurement
and Characterization
10:00am-10:30am Break
10:30am-12:00pm Session 3: Panel Session - Leveraging I-IP in the Field
12:00pm-1:30pm Lunch
01:30pm-04:00pm Session 4: Advance I-IP Solutions Test & Debug of
Embedded Logic Blocks
General
Chair: Yervant Zorian, Virage Logic
Vice General Chair: A. Ivanov, U British Columbia
Program Chair: D. Gizopoulos, U Piraeus
Finance Chair: R. Aitken, Artisan
Publicity Chair: M. Ricchetti, Intellitech
Publication Chair: P. Prinetto, Pol. di Torino
Panels Chair: H-J. Wunderlich, U of Stuttgart
Program
Committee
M. Abadir, Motorola
M. Abramovici, Dafca
D. Appello, ST Microelectronics
S. Bhawmik, Agere
J. Bordelon, HPL
W-T. Cheng, Mentor Graphics
C.J. Clark, Intellitech
K. Darbinyan, Virage Logic
S. Gupta, USC
B. Kaminska, 3MTS
H. Manhaeve, Qstar
E.J. McCluskey, Stanford U
T. McLaurin, ARM
C. Metra, U of Bologna
M. Mowji LogicVision
M. Nicolaidis, iRoC
A. Orailoglu, UC San Diego
J.M. Portal, U of Marseille
A. Raghunathan, NEC
J. Reynick, eSilicon
S. Tabatabaei, Vector12
B. Vermeulen, Philips
Workshop
Location
I-IP 2003 will be held at the Charlotte Convention Center, Charlotte,
North Carolina, USA, October 2-3, 2003, immediately following
ITC 2003 (www.itctestweek.org).
Registration
All Workshop participants require registration. Please register
using the ITC 2003 Registration Forms.
THURSDAY, October 2, 2003
Registration:
2m - 5pm
OPENING ADDRESS: 4pm - 4:30pm
Welcoming Remarks - Y. Zorian, General Chair, D. Gizopoulos, Program Chair
Session
1: Advanced I-IP Solutions for Embedded Memory Yield Improvement 4:30pm
- 6:30pm
Session Moderator: A. Ivanov, University of British Columbia
1.1 Hybrid
Infrastructure-IP for Yield Ramp-Up
Davide Appello, Alessandra Fudoli, Vincenzo Tamcorre,
ST Microelectronics, Paolo Bernardi, Maurizio Rebaudengo,
Matteo Sonza Reorda, Politecnico di Torino
1.2 Optimizing
Repair Efficiency based on Integrated STAR Memory System Methodology
Karen Darbinyan, Avetik Yessayan, Yervant Zorian, Virage Logic
1.3 Reconfigurable
At-Speed Built-In Self-Analyzer for Word Oriented Memories
Xiaogang Du, University of Iowa, Wu-Tung Cheng, Nilanjan Mukherjee, Mentor Graphics,
Sudhakar M. Reddy, University of Iowa
1.4 eDRAM
Diagnosis: An Embedded Measurement Function for Capacitor
J.M. Portal, University of Marseille, A. Lopez, D. Nee, ST Microelectronics
DISCUSSION
PANEL:
Rubin Parekhji, Texas Instruments,H-J Wunderlich, Univ of Stuttgart
RECEPTION:
7:00pm - 9:00pm
FRIDAY, October 3, 2003
Continental Breakfast: 7am - 8am
Session
2: Embedding I-IP for Configuration, Measurement and Characterization
8:00am - 10:00am
Session Moderator: Sang Baeg, Cisco
2.1 One-Bit
Global Embedded Bus
Sassan Tabatabaei,
Neil Messmer, Yong Luo, Andre Ivanov, Vector 12,
University of British Columbia
2.2 Infrastructure
Floating IP Modules Closing the Gap between ATE and DFT
Bozena Kaminska, 3MTS, Ewa Sokolowska, Pultronics, Chafik Behidj, Chartered
Semiconductor Manufacturing
2.3 Infrastructure
IP for Programming and Test of in-system Memory Devices
Michael Ricchetti,
CJ Clark, Intellitech
2.4 Methodology
and Design IP for RFCMOS Process Characterization and Performance Optimization
Jim Bordelon, Eric Wolf, John Garcia, HPL Technologies
DISCUSSION
PANEL:
Magdy Abadir,
Motorola
Sybille Hellebrand, University of Innsbruck
Coffee Break 10am - 10:30am
Session 3: 10:30pm-
12:00 pm
Panel Session - Leveraging Infrastructure-IP in the Field
Co-Organized with: IEEE Design & Test of Computer
Moderator: Dean Adams, PDAT Technologies
Panelists:
Mouli Chandramouli, Virage Logic
Tapan Chakraborty, Lucent Technologies
Eric Dupont, iRoC Technologies
Mukesh Mowji, LogicVision
Michael Ricchetti, Intellitech
Lunch: 12:00pm - 1:30pm
Session 4: Advance I-IP
Solutions Test & Debug of Embedded Logic Blocks
Session Moderator:
Cecilia Metra, University of Bologna 1:30pm - 4pm
4.1 Automatic Generation
of Breakpoint Hawdware for Silicon Debug
Zalfany Urfianto,
Royal Institute of Technology,
Stockholm; Sandeep Kumar Goel, Bart Vermeulen, Philips
Research Laboratories
4.2 Standard Cells as
Infrastructure IP
Rob Aitken, Artisan
Components
4.3 Test Response Compression
in the Presence of Any Number of Unknowns
Erik Volkerink, Stanford University, Agilent;
Subhasish Mitra, Intel
4.4 A Reconfigurable
Infrastructure IP Platform for SoCs,
Miron Abramovici, DAFCA
DISCUSSION PANEL:
Xinli Gu, Cisco
Joseph Reynick, eSilicon
Tel: +1-540-937-8280, Fax: +1-540-937-7848, Email: tttc@computer.or