Scope
The higher level of manufacturing susceptibility and field reliability in today’s
SoC require enhanced detection, diagnosis and yield optimization solutions.
These solutions necessitate incorporating on-chip infrastructure IP blocks,
in addition to the functionality of the SoC. The Infrastructure IP leverages the
manufacturing knowledge and feeds back the information into the design phase.
This workshop analyzes this key trend and gives the chance to describe a
range of infrastructure IP for today's System-on-Chip (SoC) designs. This includes
infrastructure IP for test, diagnosis, timing measurement, debugging, test,
repair, and fault tolerance.

Areas of Interest include but are not limited to
• Embedded diagnosis IP
• Design for Manufacturability
• Built-in Repair Analysis and Built-in Self-Repair
• Yield enhancement IP
• Built-in monitors and embedded measurement functions
• Embedded Test solutions (BIST)
• On-line error detection and correction blocks
• Transient error protection hardware
• Process monitoring IP
• Silicon debug infrastructure

I-IP workshop is sponsored by the IEEE Computer Society Test Technology Technical
Council (TTTC). For more information on I-IP, visit the workshop website at
http://www.unipi.gr/iip