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IEEE TTTC Test Technology Educational Program (TTEP) 2002 |
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Two TTEP 2002 tutorials are offered on Sunday May, 26th on emerging test technology topics. |
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Tutorial 1
This tutorial presents state-of-the-art embedded test technology, practices and automation tools. It covers guidelines for design of BIST-able cores, techniques for random pattern testability, as well as BIST architectures for random logic and memory arrays. It also presents new embedded test methodologies based on deterministic patterns, such as LFSR reseeding, OPMISR, Smart BIST, and Embedded Deterministic Test, developed specifically to reduce the volume of test data and test time without modification of system logic. Special emphasis is placed on issues related to at-speed testing. The material is illustrated with many applications and case studies. Attendees receive hard copies and a CD-ROM of the presented material.
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Tutorial 2 Beginning with a keynote
speech at the 1999 International Test Conference and the 1999 International
Technology Roadmap for Semiconductors, the concepts of structural testing,
DFT-testers, and Test Resource Partitioning have experienced a large increase
in publicity. Advanced scan-based logic test techniques are now emerging
in practice to address the issues of testing complex system-level products
using very deep sub-micron technologies. For further information about TTTC TTEP 2002 check: http://tab.computer.org/tttc/teg/ttep. |
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