7th IEEE ETW’02
May 26 – May 29, 2002
Corfu, Greece

Technical Program

SUNDAY, May 26, 2002

8:00 – 9:00 : TUTORIALS AND WORKSHOP REGISTRATIONS

9:00 – 17:30 : TUTORIALS

Tutorial 1: Embedded Test for Low-Cost Manufacturing

Presenter: J. Rajski, Mentor Graphics (USA)

Tutorial 2: Scan-Based Logic Test: Fundamentals and Recent Developments

Presenter: B. Koenemann, IBM (USA)

16:00 – 18:30 : WORKSHOP REGISTRATION

18:30 – 20:00 : WELCOME RECEPTION

MONDAY, May 27, 2002

7:30 – 8:30 WORKSHOP REGISTRATION

8:30 – 10:00 OPENING SESSION

Welcome
D. Gizopoulos – University of Piraeus (Greece)
A. Paschalis – University of Athens (Greece)
General Co-Chairs

Program Introduction
S.Hellebrand – University of Innsbruck (Austria)
Program Chair

Keynote Address
Silicon Technology Advances and Implications on Test
G. Spirakis – VP, Mobile Platforms Group,
Director of Design Technology Group, Intel, Santa Clara (USA)

Abstract: Despite dire predictions about the future of technology scaling, business
requirements continue to drive the scaling of transistors and interconnects. Within
the next five years we will see microprocessors with billion plus transistors running
near 10GHz. This is being made possible by the advances in Si manufacturing processes
and materials, and aggressive design techniques.

The increasing interconnect length combined with the number of process steps to manufacture
the chips point to a need for more targeted approach for testing interconnect defects, because,
often, they are not caught with simple stuck-at fault tests. Another phenomenon that is clouding
the landscape is the challenge in centering a design with regard to process variation. Design
centering issues are mainly addressed by numerous modeling and analysis approximations,
often leaving circuit marginality gaps that are resulting in an increasing incidence of a new class
of speed failures.

Aggressive quality and time to market requirements for the new products will require new test
techniques to catch these new sources of failures/defects and perform speed-binning on these chips.

10:00-11:00 Poster Session I and Coffee Break

BIST and TPG

Moderators: B. Rouzeyre – LIRMM
A. Hlawiczka – Silesian U. of Techn.

PI.1 Constraint Programming and Local Search with Multi-valued Logic for optimisation of Test Patterns
F.Azevedo, P.Barahona – U. Nova de Lisboa (Portugal)

PI.2 Fault Set Partition for Efficient Width Compression
E.Gizdarski – Synopsys (USA), H.Fujiwara –
Nara Inst. of Science and Technology (Japan)

PI.3 Column-Matching Based BIST Design Method
P.Fiser, J.Hlavicka – Czech Technical U. (Czech Republic)

PI.4 Distributed BIST using Intelligent Agents
L.Miclea, S. Enyedi – T. U. of Cluj-Napoca (Romania)

PI.5 Exact Static Compaction of Sequential Circuit Tests using branch-and-bound and Search State Registration
J.Raik, A.Jutman, R.Ubar – Tallinn Tech. U. (Estonia)

PI.6 On Test Data Compression and Decompression for Multiple Circuits
I.Pomeranz – Purdue U., S.M.Reddy – U. of Iowa (USA)

PI.7 ALU-based Built-In Self Test Generator for Transition Fault Testing
Y.Voyiatzis, N.Kranitis, A.Paschalis – U. of Athens (Greece), D.Gizopoulos – U. of Piraeus (Greece), C.Halatsis – U. of Athens (Greece)

PI.8 Initialization of Partially LBISTed sequential circuits
I.Vogel, M.L.Flottes, C.Landrault – LIRMM (France)

11:00-12:30 Sessions 1 and 2

Session 1: SoC Test I

Moderators: Z. Peng – Linkoping U.
A. Orailoglu – UC San Diego

1.1 Test Resource Optimization for Multisite Testing of Embedded-Core-Based SOCs Using ATE With Memory Depth Constraints
V.Iyengar – Duke U. (USA), S.K.Goel, E.J.Marinissen – Philips Research Labs (The Netherlands), K.Chakrabarty – Duke U. (USA)

1.2 Optimal Core Wrapper Width Selection and SOC Test Scheduling based on 3-D Bin Packing Algorithm
Y.Huang, S.M.Reddy – U. of Iowa (USA), W.-T.Cheng, P.Reuter, C.-C.Tsai, N.Mukherjee, O.Samman,
Y.Zaidan – Mentor Graphics (USA)

1.3 A Novel Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
S.K. Goel, E.J.Marinissen – Philips Research Labs
(The Netherlands)

Session 2 (Industrial Experiences): Memory and FPGA Testing

Moderators: E. Dupont – iRoC
A. Benso – Politecnico di Torino

2.1 NVM-BIST A Non-Volatile-Memory BIST Solution
D.Beattie, B.Cook, L.Grieve – Motorola Semicon. (UK)

2.2 Flash Memory Technology-Driven Test
J. Pineda de Gyvez – Philips Research (The Netherlands), R. Beurze – Philips ED&T (The Netherlands)

2.3 DPM Reduction on Dual-Port Caches (short paper)
S.Hamdioui, A.J. van de Goor – Delft U. of Technology (The Netherlands), M.Rodgers – Intel (USA)

2.4 AR2T: Implementing a Truly SRAM-based FPGA On-Line Concurrent Testing (short paper)
M.G.Gericota, G.R.Alves – ISEP (Portugal),
M.L.Silva, J.M.Ferreira – FEUP (Portugal)

12:30-14:00 Lunch

14:00-15:30 Sessions 3 and 4

Session 3: Defect Based Testing

Moderators: C. Metra – DEIS U. of Bologna
S. Chakravarty – Intel

3.1 Embedded Tutorial: The nature of parametric failures in CMOS ICs
J.Segura – U. of the Balearic Islands (Spain), A.Keshavarzi – Intel (USA), J.Soden – Sandia National Labs (USA), C.Hawkins – U. of New Mexico (USA)

3.2 Modeling Gate Oxide Short defects in CMOS Minimum Transistors
M.Renovell, J.M.Galliere, F.Azais,
Y.Bertrand – LIRMM (France)

3.3 An off-chip sensor circuit for transient current testing
B.Alorda – U. of the Balearic Islands (Spain),
B.Bloechel, A.Keshavarzi – Intel (USA),
J.Segura – U. of the Balearic Islands (Spain)

Session 4: Verification

Moderators: P. Prinetto – Politecnico di Torino
H.-J. Wunderlich – U. of Stuttgart

4.1 ATPG for Timing-Induced Functional Errors on Trigger Events in Hardware-Software Systems
S.Arekapudi, F.Xin, J.Peng,
I.G.Harris – U. of Massachusetts, Amherst (USA)

4.2 Provable Correct Behavioral Transformation Specifications (short paper)
G.Economakos – National Technical U. of Athens (Greece)

4.3 Mixing ATPG and Property Checking for Testing HW/SW Interfaces (short paper)
A.Fin, F.Fummi, M.Galavotti, G.Pravadelli – U. di Verona (Italy), U.Rossi, F.Toto – ST Microelec. (Italy)

4.4 A Theoretical Study of Design Rewiring Using ATPG (short paper)
A.Veneris – U. of Toronto (Canada), M.S.Abadir – Motorola (USA), M.Amiri – U. of Toronto (Canada)

15:30-16:30 Poster Session II and Coffee Break

Faults and Tests

Moderators: F. Azais – LIRMM
L. Miclea – TU of Cluj-Napoca

PII.1 Testing for Delay Faults using a Variable Supply Voltage in Combination with the Oscillation Test Method
H.J.Vermaak – Technikon Free State (South Africa), H.G.Kerkhoff – MESA+/U. of Twente
(The Netherlands)

PII.2 Digital Delay-Line Characterization Using the Oscillation Technique
O.Petre, H.G.Kerkhoff – MESA+/U. of Twente
(The Netherlands)

PII.3 How Robust can Non-Robust Delay Tests Become?
V.Meyer – ITEM/University of Bremen (Germany), A.Weigl – Philips Semiconductors (Germany),
A.Sticht, W.Anheier – ITEM/U. of Bremen (Germany)

PII.4 Design of Optimal Implicit Tests for Parametric Faults considering Errors of Test Stimuli and of Measurements
M.Pronath, H.Graeb, K.Antreich – Technical U. of Munich (Germany)

PII.5 Efficient transient simulation of faults in linear circuits using a mixed symbolic-numeric simulator
J.A. Soares Augusto, C.B.Almeida – INESC (Portugal)

PII.6 An Efficient Method of Crosstalk Fault Simulation for Clock-Delayed Domino Circuits
K.Shimizu, T.Shirai, M.Takamura, N.Itazaki – Osaka U. (Japan), K.Kinoshita – Osaka Gakuin U. (Japan)

PII.7 On Testing of Interconnect Open Faults in Combin. Logic Circuits with Stems of Large Fanout
H.Tang, S.M.Reddy – U. of Iowa (USA), I.Pomeranz – Purdue U. (USA), S.Kajihara – Kyushu Inst.of Technology (Japan), K.Kinoshita – Osaka Gakuin U. (Japan)

PII.8 High-Availability Middleware as a means to Highest Availability Using Standard HW/SW components
B.Kellerer, M.Reitenspiess – Fujitsu-Siemens Computers Munich (Germany)

16:30-18:00 Sessions 5 and 6

Session 5: BIST and TRP

Moderators: J. Rajski – Mentor Graphics
P. Girard – LIRMM

5.1 Dependable Testing of Compactor MISR: an Imperceptible Problem?
A.Hlawiczka, M.Kopec – Silesian U. of Tech. (Poland)

5.2 RESPIN++- Deterministic Embedded Test
L.Schäfer, R.Dorsch, H.-J.Wunderlich –
U. of Stuttgart (Germany)

5.3 Reducing Synchronization Overhead in Test Data Compression Environments (short paper)
P.T.Gonciari, B.Al-Hashimi – U. of Southampton (UK), N.Nicolici – McMaster U. (Canada)

5.4 Optimizing Mask-Based RTL Test Preparation of Digital Systems (short paper)
M.B.Santos, I.C.Teixeira and J.P.Teixeira – IST/INESC-ID (Portugal)

Session 6 (Industrial Experiences): RF and Low-Cost Testing

Moderators: M. Kessler – IBM
P. Muhmenthaler – Infineon

6.1 Test Effectiveness: A Metric for Comparing Apples to Oranges in Electronics Test
T.Ragland, A. Poelderl – Agilent (USA)

6.2 DUT board design considerations and techniques for parallel quad-site testing of Radio Frequency – System On a Chip devices (short paper)
S.Beresten, K.Schaub, D.Rishavy – Agilent (Germany)

6.3 Parameters for Open Architecture Low-cost Test Systems (short paper)
B.G.West – Schlumberger (USA)

19:00 Dinner

20:30 – 22:00 Evening Breakout Session

Moderator:

C. Landrault – LIRMM

The participants will join one of the "breakout groups" to brainstorm, in a friendly atmosphere, on one of the following topics:

• Low Power Test: Does Anybody Care!
• How can test help in getting and keeping the yield high, even when the process changes?
• Functional test: how much is enough and when should it be used?
• Will analogue and mixed-signal BIST ever become ripe?

TUESDAY, May 28, 2002

08:30-10:00 Sessions 7 and 8

Session 7: Dependability and Virtual Test

Moderators: J. Tyszer – Poznan Tech. U
E.-J. Marinissen – Philips

7.1 Reducing the VHDL-Based Fault Injection Simulation Time in a Distributed Environment
F.Rodriguez, J.C.Campelo, J.J.Serrano –
U. Politecnica de Valencia (Spain)

7.2 On-Line Self-Repair of FIR Filters
A.Benso, S.Di Carlo, G.Di Natale, P.Prinetto – Politecnico di Torino (Italy)

7.3 How Virtual Test is Implemented in the Industrial Practice - A Case Study
M.Rona, G.Krampl – Infineon (Austria)

Session 8 (Industrial Experiences): Debug and Diagnosis

Moderators: B. Bennetts – Bennetts Associates
B. Al-Hashimi – U. of Southampton

8.1 Embedded Tutorial: Embedded Memory Test, Debug and Repair, using CTL
Y.Zorian – Viragelogic (USA),
R.Kapur – Synopsys (USA)

8.2 On a statistical fault diagnosis approach enabling fast yield ramp-up
C. Hora – Eindhoven University of Technology
(The Netherlands), R. Segers, S. Eichenberger –
Philips Semiconductors (The Netherlands), M. Lousberg – Philips Research Labs (The Netherlands)

8.3 On the Diagnostic Properties of PCB/MCM Interconnections' Testing Algorithms
A.Kristof – Silesian U. of Technology (Poland)

10:00-11:00 Poster Session III and Coffee Break

Analog and Mixed Signal Testing

Moderators: B. Straube – EAS/IIS FhG
W. Anheier – U. of Bremen

PIII.1 Comparison of Methods for Testing of Analog-to-digital Converters
J.Holub, M.Kubin – Czech Technical U.
(Czech Republic)

PIII.2 Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-Up Analogue Fault Simulation
Y.Kýlýç, M.Zwolinski – U. of Southampton (UK)

PIII.3 Experimental test infrastructure supporting IEEE 1149.4 Standard
U.Kac, F.Novak – Jozef Stefan Inst. (Slovenia), F.Azais, P.Nouet, M.Renovell – LIRMM (France)

PIII.4 Requirements and Strategy for Analogue Chip Repair
A. Lechner, A. Richardson – Lancaster U.(UK),
B. Hermes – Philips Semiconductors (UK)

PIII.5 A Novel Approach for Modeling Behavior of Analog and Mixed-Signal Circuits Based on an Operation-Region Model
Y.Miura – Tokyo Metropolitan U. (Japan)

PIII.6 Time- versus Frequency-Domain Methods for High Resolution ADC Testing
M.Andrle, J.Holub, K.Al-Iriany, J.Vedral –
Czech Technical U. (Czech Republic)

PIII.7 Design of Digital Window Comparators and Implementation within Mixed-Signal DfT Schemes
D.De Venuto – Politecnico di Bari (Italy), M.J.Ohletz – Alcatel Microelectronics (Belgium),
B.Riccò – U. di Bologna (Italy)

11:00-12:30 Sessions 9 and 10

Session 9: Delay Testing

Moderators: M.Sonza Reorda – Politecnico di Torino
K.Kinoshita – Osaka Gakuin U.

9.1 Novel ATPG Algorithms for Transition Faults
X.Liu, M.S.Hsiao – Virginia Tech (USA), S.Chakravarty, P.J.Thadikaran – Intel (USA)

9.2 On Selecting Testable Paths in Scan Designs
Y.Shao, S.M.Reddy – U. of Iowa (USA),
I.Pomeranz – Purdue U. (USA),
S.Kajihara – Kyushu Inst. of Technology (Japan)

9.3 A Path Delay Fault Simulation System
S.Kundu, C.Tirumurti, R.Jayabharathi,
P.Parvathala – Intel (USA)

Session 10 (Industrial Experiences): Board Testing

Moderators: M. Vergniault – ST Microelectronics
R. Galivanche – Intel

10.1 Embedded Tutorial: Review of Board and System Test Techniques: the Impact of BGA Packaging and Boundary Scan
M.Lobetti-Bodoni – Siemens ICN (Italy),
B.Bennetts – Bennetts Associates (UK)

10.2 Status Report on IEEE P1581 SCITT Standardization
L. van de Logt, F. de Jong, –
Philips Research (The Netherlands)

12:30-14:00 Lunch

14:00-15:30 Sessions 11 and 12

Session 11: Mixed Signal Testing

Moderators: A. Osseiran – IMS
M. Renovell – LIRMM

11.1 Test Generation for Mixed-Signal Circuits Using Testability Analysis
M.Stancic, H.G.Kerkhoff –
MESA+/U. of Twente (The Netherlands)

11.2 Sensitivity Analysis Based Tolerance-Box Generation and Propagation in Mixed-Signal SoC Testing
L.Fang, H.G.Kerkhoff –
MESA+/U. of Twente (The Netherlands)

11.3 Structural Fault Driven Test Specifications Reduction for Analog Circuits
S.-J.Chang, C.L.Lee – National Chiao Tung U. (Taiwan, ROC), J.E.Chen – Chung-Hua U. (Taiwan, ROC)

Session 12 (Industrial Experiences): SoC Test II

Moderators: B. Koenemann – IBM
A. Veneris – U. of Toronto

12.1 Multi-TAP Controller Architecture for Digital System Chips
B.Vermeulen, T.Waayers – Philips Research Labs
(The Netherlands), S.Bakker – Philips Semiconductors
(The Netherlands)

12.2 Adapting an SoC to ATE Concurrent Test Capabilities
M.Fischer – Agilent (Germany), R.Dorsch, R.H.Rivera, H.-J.Wunderlich – U. of Stuttgart (Germany)

12.3 Embedded CPU Test Strategies
P.Hughes, P.Harrod, G.Campbell – ARM (UK)

15:30-16:00 Report on Breakout Sessions

Moderator:

C. Landrault – LIRMM

16:30 – 24:00 Social Event

WEDNESDAY, May 29, 2002

08:30-10:00 Sessions 13 and 14

Session 13: System Test and Debug

Moderators: R. Ubar – Tallinn Technical U.
M. Santos – INESC Lisboa

13.1 Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
S.K.Goel, B.Vermeulen – Philips Research Labs
(The Netherlands)

13.2 A Layered Architecture for System Test Design
A.Baldini, A.Benso, P.Prinetto – Politecnico di Torino (Italy), S.Mo, A.Taddei – Magneti Marelli (Italy)

13.3 System Level Testing of Virtual Switch
(Re-) Configuration over IP
T.Margaria – METAFrame Technologies (Germany), O.Niese, B.Steffen – U. of Dortmund (Germany), A.Erochok – Siemens (Germany)

Session 14 (Industrial Experiences): Bridging Faults and Current Test

Moderators: C. Hawkins – U. of New Mexico
J. Figueras – UP Catalunya

14.1 Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
J.Bradford, H.Delong – Micronas (Germany),
I.Polian, B.Becker – U. of Freiburg (Germany)

14.2 Experimental Evaluation of Scan Bridge Tests
S.Chakravarty, A.Jain, N.Radhakrishnan,
E.W.Savage, S.T.Zachariah – Intel (USA)

14.3 A Real world Application Used To Implement A True IDDQ Based Test Strategy (short paper)
H.Manhaeve – Q-Star Test (Belgium), J.S.Vaccaro, L.Benecke, D.Prystasz – Motorola (USA)

14.4 Comparison of Iddq Testing and Very-Low Voltage Testing (short paper)
B.Kruseman – Philips Research Labs (The Netherlands)

10:00-11:00 Poster Session IV and Coffee Break

Memories, Models and More

Moderators: C. Robach – ESISAR
R. Dorsch – U. of Stuttgart

PIV.1 Selection of Validation Vectors According to the Black-Box Model
V.Jusas, K.Paulikas, R.Seinauskas – Kaunas U. of Technology (Lithuania)

PIV.2 An Automated Geometric Defect Diagnosis Methodology for EEPROM Cell (AGDE)
J.M.Portal, L.Forli, H.Aziza – U. of Marseille (France), D.Née – ST-Microelectronics (France)

PIV.3 SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms
A.Jutman, J.Raik, R.Ubar – Tallinn Technical U. (Estonia)

PIV.4 Reducing Hierarchical Test Path Cost via Modular Test Requirement Analysis
Y.Makris – Yale U. (USA), A.Orailoglu –
U. of California San Diego (USA)

PIV.5 Minimizing the Overhead of Simulation on the Coverage-directed Verification
Y.Kim, K.Ryoo, S.Kim, H.Cho – Electronics and Telecommunications Research Institute (Korea)

PIV.6 Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
I.Polian – U. of Freiburg (Germany), I.Pomeranz – Purdue U. (USA), B.Becker – U. of Freiburg (Germany)

PIV.7 Summarizing a new approach to design reliable Speech Recognition Systems
F.Vargas, R.D.Fagundes, D.Barros Jr –
Catholic U.-PUCRS (Brazil)

11:00-12:30 Sessions 15 and 16

Session 15: Testing Data Converters and PLLs

Moderators: F. Novak – Jozef Stefan Institute
M. Lobetti-Bodoni – Siemens ICN

15.1 A Statistical Successive Approximation Approach for DAC/ADC Code Edge Estimation
J.W.Lin, C.L.Lee – National Chiao Tung U. (Taiwan, ROC), J.-E. Chen – Chung Hwa U. (Taiwan, ROC)

15.2 A High Accuracy Triangle-Wave Signal Generator for On-Chip ADC Testing
S.Bernard, F.Azaïs, Y.Bertrand, M.Renovell –
LIRMM (France)

15.3 Investigations For Minimum Invasion Digital Only Built In "Ramp" Based Test Techniques for Charge Pump PLL’s
M.J.Burbidge – Lancaster U. (UK), F.Poullet – Dolphin Integration (France), J.Tijou – Philips Semiconductors (UK), A.Richardson – Lancaster U. (UK)

Session 16 (Industrial Experiences): DFT and BIST

Moderators: J.P. Hayes – U. of Michigan
B. Becker – U. of Freiburg

16.1 Synchronous Full-Scan for Asynchronous Handshake Circuits
F. te Beest – MESA+/U. of Twente (The Netherlands), A.Peeters – Philips Research Labs (The Netherlands), K. van Berkel – Eindhoven U. of Technology
(The Netherlands), H.G.Kerkhoff – MESA+/U. of Twente (The Netherlands)

16.2 Combining Deterministic Logic BIST with Test Point Insertion
H.Vranken – Philips Research Labs (The Netherlands), F.Meister, H.-J.Wunderlich – U. of Stuttgart (Germany)

16.3 Hierarchical DFT Synthesis Flow using timing and physical abstractions (short paper)
F.Neuveux, S.Duggirala, L.Guiller – Synopsys (USA)

16.4 A Novel Approach to Design Rule Checking for Test-Model based Hierarchical DFT Synthesis (short paper)
S.Ramnath, M.Hirech – Synopsys (USA)

12:30-14:00 Lunch

14:00-15:30 Session 17

Session 17: Power Conscious Testing

Moderators: R. Segers – Philips
A. Richardson – Lancaster U.

17.1 Dynamic Test Data Transformations for Average and Peak Power Reductions
O.Sinanoglu, I.Bayraktaroglu, A.Orailoglu –
U. of California San Diego (USA)

17.2 Scan Cell Ordering for Low Power Scan Testing
Y.Bonhomme, P.Girard, C.Landrault, S.Pravossoudovitch – LIRMM (France)

17.3 Power Constrained Preemptive TAM Scheduling
E.Larsson, H.Fujiwara –
Nara Inst. of Science and Technology (Japan)

15:30 Closing Session